drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

32

#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

44

#define mmUVD_GPCOM_VCPU_DATA1 0x3BC5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

32

#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

32

#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

32

#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

58

#define mmUVD_GPCOM_VCPU_DATA1 0x03c5

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

142

#define mmUVD_GPCOM_VCPU_DATA1 0x03c5

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

814

#define mmUVD_GPCOM_VCPU_DATA1 0x0585

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

515

#define mmUVD_GPCOM_VCPU_DATA1 0x0091

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

831

#define mmUVD_GPCOM_VCPU_DATA1 0x0091