drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

31

#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

43

#define mmUVD_GPCOM_VCPU_DATA0 0x3BC4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

31

#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

31

#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

31

#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

56

#define mmUVD_GPCOM_VCPU_DATA0 0x03c4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

140

#define mmUVD_GPCOM_VCPU_DATA0 0x03c4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

812

#define mmUVD_GPCOM_VCPU_DATA0 0x0584

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

513

#define mmUVD_GPCOM_VCPU_DATA0 0x0090

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

829

#define mmUVD_GPCOM_VCPU_DATA0 0x0090