drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

42

#define mmUVD_CGC_GATE 0x3d2a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

35

#define mmUVD_CGC_GATE 0x3D2A

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

42

#define mmUVD_CGC_GATE 0x3d2a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

48

#define mmUVD_CGC_GATE 0x3d2a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

64

#define mmUVD_CGC_GATE 0x3d2a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

144

#define mmUVD_CGC_GATE 0x052a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

304

#define mmUVD_CGC_GATE 0x052a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

504

#define mmUVD_CGC_GATE 0x01ea

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

497

#define mmUVD_CGC_GATE 0x0088

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

813

#define mmUVD_CGC_GATE 0x0088