drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_d.h

44

#define mmUVD_CGC_CTRL 0x3d2c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h

34

#define mmUVD_CGC_CTRL 0x3D2C

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

44

#define mmUVD_CGC_CTRL 0x3d2c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h

50

#define mmUVD_CGC_CTRL 0x3d2c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

66

#define mmUVD_CGC_CTRL 0x3d2c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h

146

#define mmUVD_CGC_CTRL 0x052c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

308

#define mmUVD_CGC_CTRL 0x052c

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h

508

#define mmUVD_CGC_CTRL 0x01ec

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

501

#define mmUVD_CGC_CTRL 0x008a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h

817

#define mmUVD_CGC_CTRL 0x008a