drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5213

#define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4872

#define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2731

#define mmSPI_COMPUTE_QUEUE_RESET 0x11db

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2959

#define mmSPI_COMPUTE_QUEUE_RESET 0x11db

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2915

#define mmSPI_COMPUTE_QUEUE_RESET 0x11db

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1430

#define mmSPI_COMPUTE_QUEUE_RESET 0x31db

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1447

#define mmSPI_COMPUTE_QUEUE_RESET 0x31db

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1626

#define mmSPI_COMPUTE_QUEUE_RESET 0x31db

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1594

#define mmSPI_COMPUTE_QUEUE_RESET 0x31db