drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

1466

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x07a7

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

1512

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x078f

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

387

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

356

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

467

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

565

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h

468

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h

468

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x018f

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h

464

#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7