drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

1383

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0747

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

1424

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0737

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

364

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

328

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

429

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

530

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h

384

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h

384

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0137

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h

380

#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147