drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

1215

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

1246

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

342

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

301

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

390

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

494

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h

214

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h

214

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087

drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h

210

#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087