drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

55

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

62

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

228

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

165

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

162

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

299

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

80

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h

78

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h

80

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h

80

#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021