drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

1015

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

1599

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

1243

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

1205

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

1149

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

1159

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

1131

#define mmMCIF_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

958

#define mmMCIF_CONTROL_BASE_IDX 2