drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

79

#define mmSDMA0_PHASE1_QUANTUM 0x002d

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

86

#define mmSDMA0_PHASE1_QUANTUM 0x002d

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

240

#define mmSDMA0_PHASE1_QUANTUM 0x3415

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

177

#define mmSDMA0_PHASE1_QUANTUM 0x3415

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

175

#define mmSDMA0_PHASE1_QUANTUM 0x3415

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

312

#define mmSDMA0_PHASE1_QUANTUM 0x3415

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

104

#define mmSDMA0_PHASE1_QUANTUM 0x002d

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h

102

#define mmSDMA0_PHASE1_QUANTUM 0x002d

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h

104

#define mmSDMA0_PHASE1_QUANTUM 0x002d

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h

104

#define mmSDMA0_PHASE1_QUANTUM 0x002d