drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

77

#define mmSDMA0_PHASE0_QUANTUM 0x002c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

84

#define mmSDMA0_PHASE0_QUANTUM 0x002c

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h

239

#define mmSDMA0_PHASE0_QUANTUM 0x3414

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h

176

#define mmSDMA0_PHASE0_QUANTUM 0x3414

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h

174

#define mmSDMA0_PHASE0_QUANTUM 0x3414

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h

311

#define mmSDMA0_PHASE0_QUANTUM 0x3414

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

102

#define mmSDMA0_PHASE0_QUANTUM 0x002c

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h

100

#define mmSDMA0_PHASE0_QUANTUM 0x002c

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h

102

#define mmSDMA0_PHASE0_QUANTUM 0x002c

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h

102

#define mmSDMA0_PHASE0_QUANTUM 0x002c