drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

9355

#define mmRLC_UCODE_CNTL 0x4c27

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

9167

#define mmRLC_UCODE_CNTL 0x4c27

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

6021

#define mmRLC_UCODE_CNTL 0x4c27

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

6243

#define mmRLC_UCODE_CNTL 0x4c27

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

6207

#define mmRLC_UCODE_CNTL 0x4c27

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1179

#define mmRLC_UCODE_CNTL 0x30D2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1271

#define mmRLC_UCODE_CNTL 0x30e7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1284

#define mmRLC_UCODE_CNTL 0x30e7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1382

#define mmRLC_UCODE_CNTL 0xec27

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1384

#define mmRLC_UCODE_CNTL 0xec27