Symbol: mmRLC_SPM_UTCL1_CNTL
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
9561
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
9411
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
6225
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
6447
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
6423
#define mmRLC_SPM_UTCL1_CNTL 0x4cb5