drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

9385

#define mmRLC_PG_CNTL 0x4c43

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

9219

#define mmRLC_PG_CNTL 0x4c43

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

6037

#define mmRLC_PG_CNTL 0x4c43

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

6259

#define mmRLC_PG_CNTL 0x4c43

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

6235

#define mmRLC_PG_CNTL 0x4c43

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1165

#define mmRLC_PG_CNTL 0x30D7

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1275

#define mmRLC_PG_CNTL 0x3103

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1288

#define mmRLC_PG_CNTL 0x3103

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1386

#define mmRLC_PG_CNTL 0xec43

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1388

#define mmRLC_PG_CNTL 0xec43