drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

9301

#define mmRLC_MEM_SLP_CNTL 0x4c06

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

9109

#define mmRLC_MEM_SLP_CNTL 0x4c06

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

5969

#define mmRLC_MEM_SLP_CNTL 0x4c06

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

6191

#define mmRLC_MEM_SLP_CNTL 0x4c06

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

6155

#define mmRLC_MEM_SLP_CNTL 0x4c06

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1156

#define mmRLC_MEM_SLP_CNTL 0x30D8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1247

#define mmRLC_MEM_SLP_CNTL 0x30c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1260

#define mmRLC_MEM_SLP_CNTL 0x30c6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1349

#define mmRLC_MEM_SLP_CNTL 0xec06

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1351

#define mmRLC_MEM_SLP_CNTL 0xec06