drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

6057

#define mmRLC_LB_INIT_CU_MASK 0x4c4f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

6279

#define mmRLC_LB_INIT_CU_MASK 0x4c4f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

6255

#define mmRLC_LB_INIT_CU_MASK 0x4c4f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1151

#define mmRLC_LB_INIT_CU_MASK 0x3107

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1287

#define mmRLC_LB_INIT_CU_MASK 0x310f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1300

#define mmRLC_LB_INIT_CU_MASK 0x310f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1400

#define mmRLC_LB_INIT_CU_MASK 0xec4f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1400

#define mmRLC_LB_INIT_CU_MASK 0xec4f