drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

9293

#define mmRLC_CNTL 0x4c00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

9103

#define mmRLC_CNTL 0x4c00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

5963

#define mmRLC_CNTL 0x4c00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

6185

#define mmRLC_CNTL 0x4c00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

6149

#define mmRLC_CNTL 0x4c00

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

1136

#define mmRLC_CNTL 0x30C0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

1240

#define mmRLC_CNTL 0x30c0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

1253

#define mmRLC_CNTL 0x30c0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

1342

#define mmRLC_CNTL 0xec00

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

1345

#define mmRLC_CNTL 0xec00