drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

2023

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

10550

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

12865

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

11436

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

12698

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

9219

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

11534

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

5538

#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2