drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

69

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

73

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

67

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

73

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

73

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

70

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

77

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

94

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

9865

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

10708

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

7932

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

9564

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

4970

#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f