drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4943

#define mmCP_PQ_STATUS 0x1e58

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4604

#define mmCP_PQ_STATUS 0x1e58

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2601

#define mmCP_PQ_STATUS 0x10b8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2871

#define mmCP_PQ_STATUS 0x10b8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2805

#define mmCP_PQ_STATUS 0x10b8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

310

#define mmCP_PQ_STATUS 0x30b8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

313

#define mmCP_PQ_STATUS 0x30b8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

345

#define mmCP_PQ_STATUS 0x30b8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

345

#define mmCP_PQ_STATUS 0x30b8