Symbol: mmCP_HQD_EOP_CONTROL_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
5386
#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
5021
#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2902
#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
3130
#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
3086
#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0