Symbol: mmCPC_UTCL1_STATUS_BASE_IDX
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
5160
#define mmCPC_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
4827
#define mmCPC_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
2668
#define mmCPC_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
2920
#define mmCPC_UTCL1_STATUS_BASE_IDX 0
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
2854
#define mmCPC_UTCL1_STATUS_BASE_IDX 0