drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

1021

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

927

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

593

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

555

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

483

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

499

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

467

#define mmCC_DC_PIPE_DIS_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

300

#define mmCC_DC_PIPE_DIS_BASE_IDX 2