drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

1483

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

1805

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

1449

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h

216

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

1411

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

1355

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

1365

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

1337

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

1164

#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2