drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h

6031

#define mmD5VGA_CONTROL 0xfa

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h

6108

#define mmD5VGA_CONTROL 0xfa

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h

7782

#define mmD5VGA_CONTROL 0xfa

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

644

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

1045

#define mmD5VGA_CONTROL 0x00FA

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h

5148

#define mmD5VGA_CONTROL 0xfa

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

454

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

122

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

142

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

104

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

190

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

122

#define mmD5VGA_CONTROL 0x003a

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

107

#define mmD5VGA_CONTROL 0x003a