drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h

6027

#define mmD1VGA_CONTROL 0xcc

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h

6104

#define mmD1VGA_CONTROL 0xcc

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h

7778

#define mmD1VGA_CONTROL 0xcc

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

574

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

1041

#define mmD1VGA_CONTROL 0x00CC

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h

5144

#define mmD1VGA_CONTROL 0xcc

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h

408

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

52

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

112

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h

34

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h

168

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h

52

#define mmD1VGA_CONTROL 0x000c

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

37

#define mmD1VGA_CONTROL 0x000c