drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

2219

#define mmCP_RB_WPTR_POLL_CNTL 0x0f62

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

2302

#define mmCP_RB_WPTR_POLL_CNTL 0x0f62

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

217

#define mmCP_RB_WPTR_POLL_CNTL 0x01c2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

217

#define mmCP_RB_WPTR_POLL_CNTL 0x01c2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

211

#define mmCP_RB_WPTR_POLL_CNTL 0x01c2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

524

#define mmCP_RB_WPTR_POLL_CNTL 0x21C2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

513

#define mmCP_RB_WPTR_POLL_CNTL 0x21c2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

526

#define mmCP_RB_WPTR_POLL_CNTL 0x21c2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

579

#define mmCP_RB_WPTR_POLL_CNTL 0x21c2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

579

#define mmCP_RB_WPTR_POLL_CNTL 0x21c2