drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4763

#define mmCP_RB_WPTR 0x1df4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4416

#define mmCP_RB_WPTR 0x1df4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2422

#define mmCP_RB_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2699

#define mmCP_RB_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2637

#define mmCP_RB_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

520

#define mmCP_RB_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

215

#define mmCP_RB_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

215

#define mmCP_RB_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

239

#define mmCP_RB_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

240

#define mmCP_RB_WPTR 0x3045