drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4773

#define mmCP_RB2_WPTR 0x1df8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4426

#define mmCP_RB2_WPTR 0x1df8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2432

#define mmCP_RB2_WPTR 0x1058

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2709

#define mmCP_RB2_WPTR 0x1058

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2647

#define mmCP_RB2_WPTR 0x1058

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

511

#define mmCP_RB2_WPTR 0x3069

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

217

#define mmCP_RB2_WPTR 0x3069

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

217

#define mmCP_RB2_WPTR 0x3069

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

241

#define mmCP_RB2_WPTR 0x3069

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

242

#define mmCP_RB2_WPTR 0x3069