drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4799

#define mmCP_RB2_BASE 0x1e05

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4452

#define mmCP_RB2_BASE 0x1e05

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2456

#define mmCP_RB2_BASE 0x1065

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2733

#define mmCP_RB2_BASE 0x1065

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2671

#define mmCP_RB2_BASE 0x1065

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

506

#define mmCP_RB2_BASE 0x3065

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

200

#define mmCP_RB2_BASE 0x3065

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

200

#define mmCP_RB2_BASE 0x3065

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

224

#define mmCP_RB2_BASE 0x3065

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

225

#define mmCP_RB2_BASE 0x3065