drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4769

#define mmCP_RB1_WPTR 0x1df6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4422

#define mmCP_RB1_WPTR 0x1df6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2428

#define mmCP_RB1_WPTR 0x1056

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2705

#define mmCP_RB1_WPTR 0x1056

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2643

#define mmCP_RB1_WPTR 0x1056

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

505

#define mmCP_RB1_WPTR 0x3064

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

216

#define mmCP_RB1_WPTR 0x3064

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

216

#define mmCP_RB1_WPTR 0x3064

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

240

#define mmCP_RB1_WPTR 0x3064

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

241

#define mmCP_RB1_WPTR 0x3064