drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4791

#define mmCP_RB1_CNTL 0x1e01

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4444

#define mmCP_RB1_CNTL 0x1e01

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2450

#define mmCP_RB1_CNTL 0x1061

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2727

#define mmCP_RB1_CNTL 0x1061

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2665

#define mmCP_RB1_CNTL 0x1061

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

501

#define mmCP_RB1_CNTL 0x3061

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

203

#define mmCP_RB1_CNTL 0x3061

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

203

#define mmCP_RB1_CNTL 0x3061

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

227

#define mmCP_RB1_CNTL 0x3061

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

228

#define mmCP_RB1_CNTL 0x3061