drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4931

#define mmCP_RB1_BASE_HI 0x1e52

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4592

#define mmCP_RB1_BASE_HI 0x1e52

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2589

#define mmCP_RB1_BASE_HI 0x10b2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2859

#define mmCP_RB1_BASE_HI 0x10b2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2793

#define mmCP_RB1_BASE_HI 0x10b2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

199

#define mmCP_RB1_BASE_HI 0x30b2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

199

#define mmCP_RB1_BASE_HI 0x30b2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

223

#define mmCP_RB1_BASE_HI 0x30b2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

224

#define mmCP_RB1_BASE_HI 0x30b2