drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4789

#define mmCP_RB1_BASE 0x1e00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4442

#define mmCP_RB1_BASE 0x1e00

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2448

#define mmCP_RB1_BASE 0x1060

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2725

#define mmCP_RB1_BASE 0x1060

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2663

#define mmCP_RB1_BASE 0x1060

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

500

#define mmCP_RB1_BASE 0x3060

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

198

#define mmCP_RB1_BASE 0x3060

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

198

#define mmCP_RB1_BASE 0x3060

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

222

#define mmCP_RB1_BASE 0x3060

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

223

#define mmCP_RB1_BASE 0x3060