drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4761

#define mmCP_RB0_WPTR 0x1df4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4414

#define mmCP_RB0_WPTR 0x1df4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2420

#define mmCP_RB0_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2697

#define mmCP_RB0_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2635

#define mmCP_RB0_WPTR 0x1054

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

499

#define mmCP_RB0_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

214

#define mmCP_RB0_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

214

#define mmCP_RB0_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

238

#define mmCP_RB0_WPTR 0x3045

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

239

#define mmCP_RB0_WPTR 0x3045