drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4711

#define mmCP_RB0_CNTL 0x1de1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4366

#define mmCP_RB0_CNTL 0x1de1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2366

#define mmCP_RB0_CNTL 0x1041

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2643

#define mmCP_RB0_CNTL 0x1041

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2581

#define mmCP_RB0_CNTL 0x1041

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

495

#define mmCP_RB0_CNTL 0x3041

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

201

#define mmCP_RB0_CNTL 0x3041

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

201

#define mmCP_RB0_CNTL 0x3041

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

225

#define mmCP_RB0_CNTL 0x3041

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

226

#define mmCP_RB0_CNTL 0x3041