drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4929

#define mmCP_RB0_BASE_HI 0x1e51

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4590

#define mmCP_RB0_BASE_HI 0x1e51

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2587

#define mmCP_RB0_BASE_HI 0x10b1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2857

#define mmCP_RB0_BASE_HI 0x10b1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2791

#define mmCP_RB0_BASE_HI 0x10b1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

196

#define mmCP_RB0_BASE_HI 0x30b1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

196

#define mmCP_RB0_BASE_HI 0x30b1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

220

#define mmCP_RB0_BASE_HI 0x30b1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

221

#define mmCP_RB0_BASE_HI 0x30b1