drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

2227

#define mmCP_QUEUE_THRESHOLDS 0x0f78

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

2310

#define mmCP_QUEUE_THRESHOLDS 0x0f78

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

225

#define mmCP_QUEUE_THRESHOLDS 0x01d8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

225

#define mmCP_QUEUE_THRESHOLDS 0x01d8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

219

#define mmCP_QUEUE_THRESHOLDS 0x01d8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

493

#define mmCP_QUEUE_THRESHOLDS 0x21D8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

537

#define mmCP_QUEUE_THRESHOLDS 0x21d8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

550

#define mmCP_QUEUE_THRESHOLDS 0x21d8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

603

#define mmCP_QUEUE_THRESHOLDS 0x21d8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

603

#define mmCP_QUEUE_THRESHOLDS 0x21d8