drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4837

#define mmCP_PQ_WPTR_POLL_CNTL 0x1e23

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4498

#define mmCP_PQ_WPTR_POLL_CNTL 0x1e23

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2497

#define mmCP_PQ_WPTR_POLL_CNTL 0x1083

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2771

#define mmCP_PQ_WPTR_POLL_CNTL 0x1083

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2707

#define mmCP_PQ_WPTR_POLL_CNTL 0x1083

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

262

#define mmCP_PQ_WPTR_POLL_CNTL 0x3083

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

264

#define mmCP_PQ_WPTR_POLL_CNTL 0x3083

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

295

#define mmCP_PQ_WPTR_POLL_CNTL 0x3083

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

295

#define mmCP_PQ_WPTR_POLL_CNTL 0x3083