drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5375

#define mmCP_MQD_CONTROL 0x1fcb

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

5010

#define mmCP_MQD_CONTROL 0x1fcb

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2891

#define mmCP_MQD_CONTROL 0x1267

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3119

#define mmCP_MQD_CONTROL 0x1267

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3075

#define mmCP_MQD_CONTROL 0x1267

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

601

#define mmCP_MQD_CONTROL 0x3267

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

614

#define mmCP_MQD_CONTROL 0x3267

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

667

#define mmCP_MQD_CONTROL 0x3267

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

667

#define mmCP_MQD_CONTROL 0x3267