drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5305

#define mmCP_MQD_BASE_ADDR_HI 0x1faa

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4940

#define mmCP_MQD_BASE_ADDR_HI 0x1faa

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2821

#define mmCP_MQD_BASE_ADDR_HI 0x1246

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3049

#define mmCP_MQD_BASE_ADDR_HI 0x1246

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3005

#define mmCP_MQD_BASE_ADDR_HI 0x1246

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

568

#define mmCP_MQD_BASE_ADDR_HI 0x3246

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

581

#define mmCP_MQD_BASE_ADDR_HI 0x3246

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

631

#define mmCP_MQD_BASE_ADDR_HI 0x3246

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

631

#define mmCP_MQD_BASE_ADDR_HI 0x3246