drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4821

#define mmCP_MEM_SLP_CNTL 0x1e19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4484

#define mmCP_MEM_SLP_CNTL 0x1e19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2482

#define mmCP_MEM_SLP_CNTL 0x1079

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2759

#define mmCP_MEM_SLP_CNTL 0x1079

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2697

#define mmCP_MEM_SLP_CNTL 0x1079

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

455

#define mmCP_MEM_SLP_CNTL 0x3079

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

255

#define mmCP_MEM_SLP_CNTL 0x3079

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

257

#define mmCP_MEM_SLP_CNTL 0x3079

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

289

#define mmCP_MEM_SLP_CNTL 0x3079

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

289

#define mmCP_MEM_SLP_CNTL 0x3079