drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4811

#define mmCP_INT_CNTL_RING2 0x1e0c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4464

#define mmCP_INT_CNTL_RING2 0x1e0c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2472

#define mmCP_INT_CNTL_RING2 0x106c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2749

#define mmCP_INT_CNTL_RING2 0x106c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2687

#define mmCP_INT_CNTL_RING2 0x106c

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

440

#define mmCP_INT_CNTL_RING2 0x306C

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

224

#define mmCP_INT_CNTL_RING2 0x306c

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

224

#define mmCP_INT_CNTL_RING2 0x306c

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

248

#define mmCP_INT_CNTL_RING2 0x306c

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

249

#define mmCP_INT_CNTL_RING2 0x306c