drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4809

#define mmCP_INT_CNTL_RING1 0x1e0b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4462

#define mmCP_INT_CNTL_RING1 0x1e0b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2470

#define mmCP_INT_CNTL_RING1 0x106b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2747

#define mmCP_INT_CNTL_RING1 0x106b

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2685

#define mmCP_INT_CNTL_RING1 0x106b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

439

#define mmCP_INT_CNTL_RING1 0x306B

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

223

#define mmCP_INT_CNTL_RING1 0x306b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

223

#define mmCP_INT_CNTL_RING1 0x306b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

247

#define mmCP_INT_CNTL_RING1 0x306b

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

248

#define mmCP_INT_CNTL_RING1 0x306b