drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

4807

#define mmCP_INT_CNTL_RING0 0x1e0a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4460

#define mmCP_INT_CNTL_RING0 0x1e0a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2468

#define mmCP_INT_CNTL_RING0 0x106a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

2745

#define mmCP_INT_CNTL_RING0 0x106a

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

2683

#define mmCP_INT_CNTL_RING0 0x106a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

438

#define mmCP_INT_CNTL_RING0 0x306A

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

222

#define mmCP_INT_CNTL_RING0 0x306a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

222

#define mmCP_INT_CNTL_RING0 0x306a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

246

#define mmCP_INT_CNTL_RING0 0x306a

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

247

#define mmCP_INT_CNTL_RING0 0x306a