drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

7343

#define mmCP_IB1_BASE_LO 0x20cc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

6982

#define mmCP_IB1_BASE_LO 0x20cc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

4839

#define mmCP_IB1_BASE_LO 0x20cc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

5069

#define mmCP_IB1_BASE_LO 0x20cc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

5025

#define mmCP_IB1_BASE_LO 0x20cc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h

426

#define mmCP_IB1_BASE_LO 0x21CC

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

523

#define mmCP_IB1_BASE_LO 0xc0cc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

536

#define mmCP_IB1_BASE_LO 0xc0cc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

589

#define mmCP_IB1_BASE_LO 0xc0cc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

589

#define mmCP_IB1_BASE_LO 0xc0cc