drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5355

#define mmCP_HQD_SEMA_CMD 0x1fc3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4990

#define mmCP_HQD_SEMA_CMD 0x1fc3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2871

#define mmCP_HQD_SEMA_CMD 0x125f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3099

#define mmCP_HQD_SEMA_CMD 0x125f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3055

#define mmCP_HQD_SEMA_CMD 0x125f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

593

#define mmCP_HQD_SEMA_CMD 0x325f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

606

#define mmCP_HQD_SEMA_CMD 0x325f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

657

#define mmCP_HQD_SEMA_CMD 0x325f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

657

#define mmCP_HQD_SEMA_CMD 0x325f