drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5329

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4964

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2845

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3073

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3029

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

580

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

593

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

643

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

643

#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252