drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

5327

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

4962

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

2843

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

3071

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

3027

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h

579

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h

592

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h

642

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h

642

#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251